2025 NSF Research Experiences for Undergraduates (REU)

On this page:

• Dates and Topic
• Program Overview
• Application Information
• Housing and Transportation
• Faculty
• Projects
• Application

 

Dates and Topic

Research Experience Dates: June 1—August 10, 2025
Topic: Cybersecurity in Trusted Microelectronics: Addressing Challenges in Hardware Security and Resilient Supply Chains
 

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Program Overview

Secure and Trusted Systems

The summer Research Experiences for Undergraduates (REU) program, funded by the NSF Division of Computer and Network Systems, focuses on Training Research for Undergraduate Students in Secure and Trusted Systems (TRUST). It emphasizes hardware security in areas such as the Internet of Things (IoT), embedded AI security, detection and mitigation of side-channel attacks, and the security and trust of firmware and embedded systems.

Project Objectives

• Engage in trusted microelectronics research to gain practical experience in areas critical to national.
• Facilitate self-assessment for interns regarding their interests in cybersecurity and potential graduate studies.
• Acquire advanced knowledge in hardware security, encompassing hardware, software, IoT, communications, and machine/deep learning security.

Activities

• Hands-on FPGA development and simulation of CNN accelerators
• Data analysis of voltage traces captured during inference.
• Application of noise reduction techniques for accurate data interpretation.
• Exploration and implementation of countermeasures against hardware side-channel attacks.
• Design partitioning and hardware integration for enhanced security measures.

Topic Areas

• Hardware Security in Trusted System
• Side-Channel Attack and Countermeasures
• AI Hardware Security and Firmware Protection
• Embedded System Security in IoT Applications
• Research Collaboration in Secure Microelectronics Development

Award Information

• $6,500 stipend for 10 weeks
• On-campus housing included
• Food allowance
• Round-trip travel expenses up to $600 ➢ The total is approximately $9,000
   

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Application Information

Deadline: March 1, 2025
Announcement of Awards: April 1, 2025

Eligibility Requirements

• U.S. citizen or permanent resident
• Electrical engineering, computer/software engineering, computer Science, or any other related disciplines with a 3.0 or higher GPA
• Sophomore, junior, or senior
• Must graduate after September 2025

 

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Housing & Transportation

Housing

On-campus housing will be coordinated and provided for REU participants for 10 weeks. The rooms are furnished with a twin-sized bed, desk, and chair. The desk will be open 24 hours, and the participants may pick up their keys. For more housing information, please visit the Wright State Residence Life and Housing website.

Work Site

All REU students will work at the Wright State University College of Engineering and Computer Science and Air Force Institute of Technology Lab.

Transportation

RTA buses run from downtown Dayton to Wright State and from downtown to many other destinations. RTA transportation passes and schedules are available at the Wright State University Campus Store, 182 Student Union. The RTA’s phone number is 937-425-8300. All buses feature bike racks and meet ADA accessibility guidelines.

Greene CATS Public Transit’s services are open to the general public and meet ADA accessibility guidelines.

They provide two types of Demand Responsive service:

1. Scheduled Rides pick up and drop off riders at any location within Greene County with limited service to neighboring counties;
2. Flex Routes have defined routes with scheduled time points that circulate and link Greene County communities of Beavercreek, Fairborn, Xenia, and Yellow Springs. Deviations on Flex Routes up to 1/2 of a mile are available upon request. The Wright State University’s time point is located along the Orange Line flex route and is at the Student Union (shared bus stop with Greater Dayton RTA and the Raider Shuttle). Flex Route buses are also equipped with bike racks.
    

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Faculty

The project will be carried out by a team of PIs/Co-PIs with complementary expertise in cybersecurity and education.

 

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Projects

AI Hardware Trojan Design and Detection

This project equips students with comprehensive knowledge and hands-on experience in hardware security by focusing on both the creation and detection of hardware Trojans in AI accelerators.

Part 1: Trojan Design
Students will learn about the design principles of hardware Trojans, covering different abstraction levels such as gate level, RTL, and layout. They will design a simple Trojan circuit within an AI accelerator comprising a trigger and payload and observe its effect on system behavior. Using the provided HDL code, students modify the accelerator to insert the Trojan. After synthesizing the modified design onto an FPGA, they will analyze how the Trojan disrupts clock behavior during image processing, potentially leading to misclassifications.

Part 2: Trojan Detection
Students will explore side-channel analysis as a method to detect hardware Trojans. By collecting power signatures from a suspected Trojan-infected chip and comparing them to a Trojan-free reference design, students will apply machine learning-based tools to detect discrepancies in power usage. The project aims to give students hands-on experience with Trojan design, side-channel analysis, data collection, and hardware security.

Power Side-Channel Hardware Attacks and Countermeasures

This project gives students practical insights into executing power side-channel attacks on AI hardware and designing countermeasures to protect against these vulnerabilities.

Part 1: Power Side-Channel Attacks
Students will implement power side-channel attacks on a CNN accelerator running on an FPGA. They will analyze power consumption patterns using an oscilloscope to identify foreground and background image components during inference. Through voltage trace analysis, students will learn to separate these components based on power usage. They will also apply noise reduction techniques to improve data accuracy and extract image details from background pixels.

Part 2: Countermeasures Against Side-Channel Attacks
This phase teaches students how to design and implement protective strategies against side-channel attacks. They will partition the hardware design and create obfuscated variants to mask timing information and randomize execution paths. By generating FPGA bitstreams and collecting timing data, students will assess the effectiveness of these hardware countermeasures in defending against timing-based side-channel attacks.

Embedded System Security

This project introduces students to the security challenges and solutions in modern embedded systems. The focus is on hardware testing, verification, FPGA programming, and compiler integration.

Hardware Testing and Verification
Students will collaborate with the Air Force Institute of Technology (AFIT) to test and verify modules for a RISC-V embedded processor. This involves developing test software and firmware to validate processor modules and prevent errors.

Trusted Hardware Platforms on FPGA
Students will gain hands-on experience in programming Field Programmable Gate Arrays (FPGAs) using Hardware Description Languages (HDL) like VHDL. They will develop and test trusted hardware platforms, focusing on ensuring security in embedded systems.

Trusted Microprocessor Integration
Students will assist in integrating a trusted microprocessor into the LLVM compiler suite in collaboration with the Air Force Research Laboratory (AFRL). They will work on low-level assembly programming and optimize hardware instructions, ensuring their proper execution in a processor emulator. This task provides insights into compiler optimization, hardware security, and embedded system development.
 

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Application